Bias and precharging circuit for use in reading EPROM cells

ABSTRACT

The bias and precharging circuit comprises a bias part and a precharging part of the bit line together with a sensing amplifier operating by comparison of the voltage of the bit line and a dummy bit line. The precharging part includes components which turn off the bias and precharging parts as soon as the sensing amplifier has read the cell subjected to precharging. The bias part includes components for amplifying the voltage unbalance produced by bias between the bit line and the dummy bit line. It provides a current-mirror to cause said voltage unbalance independently of the precharging part.

This application is a continuation of Ser. No. 07/632,631, filed Dec.26, 1990, now abandoned, which was a continuation of Ser. No.07/274,885, filed Nov. 22, 1988, now abandoned.

BACKGROUND OF THE INVENTION

The subject of the present invention is a bias and precharging circuitfor a bit line of EPROM memory cells in CMOS technology.

Known circuits of this type used for reading cells of an EPROM memorycell matrix comprise a part designed for bias of the bit line and a partdesigned for fast precharging of said bit line. There is also provided asensing amplifier operating by comparison of the voltage of said bitline with that of a dummy bit line connected to comparison memory cellsnever subjected to programming.

Said circuits are based on the principle that bias originates in the bitline a voltage which depends on the state of conduction of the cellbeing read and is thus unbalanced with that of the dummy bit line. Theunbalance is sensed by the sensing amplifier, which converts it into areading signal indicating the state of the cell being read. Prechargingmakes reading fast.

The principal drawbacks of the abovesaid circuits are represented atpresent by high current consumption and the need for a very sensitiveand hence rather complicated sensing amplifier which would be capabaleof sensing a rather small voltage unbalance at its ends.

SUMMARY OF THE INVENTION

The object of the present invention is to realize a bias and prechargingcircuit for a bit line of EPROM memory cells in CMOS technology freefrom the aforesaid drawbacks and specifically providing very smallcurrent consumption and allowing the use of a less sensitive and hencesimpler sensing amplifier.

In accordance with the invention said object is achieved by a bias andprecharging circuit which in the first place is characterized in thatthe precharging part comprises means for turning off the bias andprecharging parts of the circuit as soon as the sensing amplifier hasread the cell subjected to precharging.

The circuit in accordance with the invention is also characterized inthat the bias part comprises a cascode amplification stage placed on thebit line to amplify the voltage unbalance caused by bias of a cell atthe input of the sensing amplifier.

Finally the circuit in accordance with the invention is characterized inthat the bias part comprises current-mirror means placed on the bit lineand the dummy bit line to cause said voltage unbalance.

As a result current consumption of the circuit is clearly reduced due tothe effect of turning off the precharging and bias parts of the circuitat the end of the time strictly necessary for the sensing amplifier toread the state of the cell.

At the same time amplification of the voltage unbalance by the cascodestage and use of a current mirror allow use of a less sensitive andhence simpler sensing amplifier.

BRIEF DESCRIPTION OF THE DRAWING

An example of a practical embodiment of the circuit in accordance withthe invention is illustrated for greater clarity in the annexed drawingwhich shows the circuit diagram thereof.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the drawing reference numbers 1 and 2 indicate a bit line and a dummybit line respectively which connect a voltage supply terminal 3 to anEPROM memory 4 with CMOS technology comprising in a known manner amatrix of memory cells selectable by means of a plurality of bit linesbranching from the bit line 1 through a decoder and a plurality of wordlines perpendicular to the bit lines as well as a plurality ofcomparison cells never subjected to programming to which is connectedthe dummy bit line 2.

With the lines 1 and 2 is associated a bias and precharging circuit madeup of a bias part 5 and a fast precharging part 6. There is alsoprovided a sensing amplifier 7 (which provides reading signal S) placedbetween respective intermediate circuit nodes 8 and 9 of the lines 1 and2.

The bias part 5 is controlled through a P channel transistor 10 whosegate receives a control signal A which constitutes the negation of acontrol signal A for the precharging part 6, both signals being emittedby an appropriately controlled generator 11.

Said bias part comprises on the dummy line 2 between the memory 4 andthe circuit node 9 an N channel transistor 12 with gate controlled by areference voltage Vref while between the circuit node 9 and the controltransistor 10 are placed in parallel two equal P channel transistors 13and 14 with gate terminals connected to respective drain terminals. Tosaid transistors 13 and 14 corresponds on the line 1, in current mirrorconfiguration, an equal P channel transistor 15 with gate terminalconnected to the common gate and drain terminals of the transistors 13and 14. Between the circuit node 8 and the memory 4, again on the bitline 1, there is placed an N channel transistor 16 controlled by thereference voltage Vref and constituting a cascode amplification stagefor the voltage unbalance which occurs between the two lines 1 and 2 inthe reading phase.

The precharging part 6 comprises a P channel control transistor 17placed between a supply terminal 18 and the memory 4 with an N channeltransistor 19 in series and controlled by the reference voltage Vref.The gate of the transistor 17 is controlled by the output of an NANDlogic port 20 which receives at one input the abovementioned controlsignal A and has another input connected to the output of a flip-flop 21made up of two NAND logic elements 22 and 23. One input of the logicelement 22 is connected to the circuit node 8 through an inverter 24.One input of the logic element 23 receives an initialization signal B.The output of said logic element 23 forms a signal C which acts on thegenerator 11 in such a manner as to switch the signals A and A to alogic level such as to turn off the precharging part 6 and the bias part5 after reading by the sensing amplifier 7. An external signal D appliedto the generator 11 is used to $tart precharging.

Between the circuit node 8 and ground there is placed an N channeltransistor 25 with gate controlled by the signal A.

In operation with the control transistor 10 in conduction thetransistors 12, 13 and 14 bias the dummy bit line 2 at an appropriatevoltage while the transistor 15 mirrors on the bit line 1 half of thecurrent flowing in the dummy bit line 2. In this manner on the line 1there is an unbalanced voltage with respect to that of the line 2 in amanner depending on the state of conduction of the cell being read. Thetransistor 16 constitutes as already mentioned a cascode circuit whichamplifies the voltage unbalance at the input of the sensing amplifier 7.

Bit line 1 is biased rapidly using the precharging part 6. At thebeginning the signal A is low so that A is high, the control transistors10 and 17 are turned off and bias part 5 is not supplied. In additionthe signal B has initialized the flip-flop 21 so as to send the signal Cto high level. Reading is initiated by the signal D which takes A tohigh level and consequently A to low level. The signal A takes thetransistor 17 into conduction while the signal A takes the transistor 10into conduction. Therefore the bias part 5 is supplied through thetransistor 10 and the bit line 1 is precharged by the precharging part 6through the transistors 17 and 19 which are mutually in series.Precharging of the bit line 1 sends to high level the circuit node 8which, through the inverter 24, switches the flip-flop 21 so as to turnoff the transistor 17 and hence the precharging part 6. The signal C,which goes to low level, is then used to send A to low level and A tohigh level thus reducing to zero the consumption of the entire circuitafter reading.

We claim:
 1. A bit line bias and precharging circuit for reading anEPROM memory cell in CMOS technology arranged on a bit line with aparallel dummy bit line, comprising a bias part connected to the memorycell and a precharging part connected to the bias part, said bias partincluding:a sense amplifier having a first input, a second input and anoutput responsive to a voltage difference between said first and secondinput; first switch means connected to said bit line and said dummy bitline and activated by an external reading control input for feeding afirst bias current to said dummy bit line, and consequently producing afirst bias voltage at said first input of the sense amplifier, and forfeeding a second bias current to said bit line and consequentlyproducing a second bias voltage dependent on the state of the memorycell being read at said second input of the sense amplifier; whereinsaid precharging part includes second switch means likewise activated bysaid reading control input for connecting the bit line to a voltagesupply to precharge the bit line at a precharged voltage value higherthan a rest value thereof and means responsive to said prechargedvoltage value on said bit line to cause deactivation of said first andsecond switch means.
 2. Circuit in accordance with claim 1, wherein saidbias part comprises a cascode amplification stage placed on the bitline.
 3. Circuit in accordance with claim 1, wherein said bias partcomprises current-mirror means connected between the bit line and thedummy bit line to cause voltage unbalance between the two lines.
 4. Abit line bias and precharging circuit for reading an EPROM memory cellhaving an associated first bit line and a second, dummy bit lineparallel to the first bit line, with each of the first bit line and thedummy bit line having a sensing terminal, comprising:control signalgeneration means for generating, in response to external input signals,activating control signals indicating that the EPROM memory cell is tobe precharged, said control signal generation means having a feedbackcontrol input and responding to a completion signal at said feedbackcontrol input to generate deactivating control signals indicating thatthe EPROM memory cell has been precharged; precharging circuit meansconnected to the control signal generating means, the feedback controlinput, and the first bit line sensing terminal, and responsive to theactivating control signals to elevate a bias voltage at the first bitline sensing terminal and including means responsive to said elevatedbias voltage value on said first bit line to generate said completionsignal at said feedback control input; bias circuit means connected tothe control signal generation means and to the first bit line and dummybit line, responding to the activating control signals, for transmittinga first bias current signal to the dummy bit line and a second biascurrent signal to the first bit line to cause the first bit lineterminal voltage to vary from the elevated bias voltage value dependingon the state of the memory cell being read.
 5. The bit line bias andprecharging circuit of claim 4 wherein the bias circuit means comprisescascode amplifier means connected between the memory cell bit line andthe first bit line sensing terminal for amplifying a state-indicatingsignal provided from the memory cell bit line for sensing at the firstbit line sensing terminal.
 6. The bit line bias and precharging circuitof claim 5 wherein the bias circuit means comprises current-mirror meansconnecting the sensing terminals of the first bit line and the dummy bitline.
 7. The bit line bias and precharging circuit of claim 4 whereinthe bias circuit means comprises current-mirror means connecting thesensing terminals of the first bit line and the dummy bit line.